1. Field of the Invention
The present invention relates to a Thin-Film Transistor (TFT) and a method of fabricating the same and more particularly, to a TFT, a TFT array substrate, and a Liquid-Crystal Display (LCD) device, and methods of fabricating them, where the etching profile of an insulating layer is controllable in an etching process. The invention is applicable not only to LCD devices, but also to plasma display devices and display devices employing organic ElectroLuminescence (EL) or the like.
2. Description of the Related Art
Generally, the LCD device comprises a TFT substrate on which TFTs are arranged in a matrix array, an opposite substrate, and a liquid crystal layer sandwiched by the TFT substrate and the opposite substrate. Pixels are defined on the TFT array substrates. The TFTS, which are arranged to correspond to the respective pixels, turn the optical paths on or off in the respective pixels, thereby displaying images on the screen of the LCD device.
In the typical fabrication method of the TFT array substrate, a gate insulating layer and a patterned semiconductor layer are formed on or over a glass plate or the like and then, a passivation layer is formed to cover the gate insulating layer and the semiconductor layer. When etching the passivation layer and the gate insulating layer, a patterned photoresist film as a mask is formed on the passivation layer. Thereafter, the passivation layer and the gate insulating layer are selectively etched to form contact holes using the mask. In this case, the etch rates of the passivation layer and the gate insulating layer are set to be approximately equal to or less than the etch rate of the photoresist film or mask, thereby forming the contact holes with tapered profiles utilizing the simultaneous etching of the mask.
To raise the production capacity of an individual etching apparatus, an etch rate may be raised by changing the etching condition in a dry etching process. In this case, however, the raised etch rate of the photoresist mask is unable to follow the raised etch rates of the passivation layer and the gate insulating layer and as a result, there is a possibility that the etching profile of the contact holes penetrating the passivation layer and the gate insulating layer is square or inverted tapered. If so, a conductive layer to be formed on the passivation layer to contact the underlying gate layer or drain layer will be divided or cut in the contact holes, resulting in point defects or the like of the LCD device.
A conventional LCD device, which is termed the first prior art, comprises a TFT array substrate 100 on which TFTs 112 are arranged, as shown in FIGS. 1 and 2. FIG. 1 is a plan view of the TFT array substrate 100 and FIG. 2 is a partial cross-sectional view thereof.
As shown in FIGS. 1 and 2, a patterned conductive gate layer 102 is formed on a transparent insulating plate 101 (i.e., a glass plate). The gate layer 102 is used to form gate lines, gate electrodes 102a, and gate terminals. On the gate layer 102 (i.e., the gate electrodes 102a), a gate insulating layer 103 is formed to cover the gate electrodes 102a. Island-shaped semiconductor layers 104 are formed to overlap with the corresponding gate electrodes 102a. On the semiconductor layers 104, a patterned conductive drain layer 105 is formed. The drain layer 105 is used to form drain lines, drain electrodes 105d, source electrodes 105s, and drain terminals. On the drain layer 105, a passivation layer 106 is formed to protect the underlying layered structure. On the passivation layer 106, a pixel electrode layer 107 as a conductive layer is formed. The pixel electrode layer 107 is used to form pixel electrodes 107a, gate terminals in gate terminal sections 111, and drain terminals in drain terminal sections 113.
The source electrodes 105s of the drain layer 105 are respectively connected to the corresponding pixel electrodes 107a formed by the pixel electrode layer 107 by way of corresponding contact holes 109a in the contact hole sections 109. The contact holes 109a are formed to penetrate the passivation layer 106 by selectively removing the same layer 106, as shown in FIG. 6B.
In the gate terminal sections 111, the passivation layer 106 and the gate insulating layer 103 are selectively removed to form contact holes 114 exposing the gate layer 102 (i.e., the gate terminals), as shown in FIG. 6A. The conductive layer 107 (i.e., the pixel electrode layer), which is located on the passivation layer 106, contacts the underlying gate layer 102 by way of the respective contact holes 114. The conductive layer 107 is connected to external terminals (not shown).
In the drain terminal sections 113, the passivation layer 106 is selectively removed to form contact holes 115 exposing the drain layer 105 (i.e., the drain terminals), as shown in FIG. 6C. The conductive layer 107 (i.e., the pixel electrode layer), which is located on the passivation layer 106, contacts the underlying drain layer 105 (i.e., the drain terminals) by way of the respective contact holes 115. The conductive layer 107 is connected to external terminals (not shown).
The TFTs 112 are formed to overlap with the corresponding island-shaped semiconductor layers 104, as shown in FIG. 2. Each of the TFT 112 comprises the gate electrode 102a formed by the gate layer 102, the drain electrode 105d formed by the drain layer 105, and the source electrode 105s formed by the drain layer 105.
As explained above, the TFT array substrate 100 of the conventional LCD device (i.e., the first prior art) has the above-described structure. In the fabrication method of the TFT array substrate 100, the passivation layer 106 (and the underlying gate insulating layer 103) are selectively removed by dry etching to form the contact holes 109a, 114, and 115, where a patterned photoresist film is used as a mask. In this etching process, the etch rate of the photoresist film is set to be equal to the etch rates of the passivation layer 106 and the gate insulating layer 103. Alternately, the etch rate of the photoresist film is set to be greater than the etch rates of the passivation layer 106 and the gate insulating layer 103. This is to make the photoresist film etched away horizontally during the etching process, thereby forming tapered etching profiles of the contact holes 109a, 114, and 115.
FIG. 3A to FIG. 6C are partial cross-sectional views showing the fabrication process steps of the TFT array substrate 100 of the first prior-art LCD device of FIGS. 1 and 2. FIGS. 3A, 4A, 5A, and 6A show the cross-sectional views of the gate terminal section 111 in FIG. 1 along the line A-A′, respectively. FIGS. 3B, 4B, 5B, and 6B show the cross-sectional views of the contact hole section 109 of the TFT 112 in FIG. 1 along the line B-B′, respectively. FIGS. 3C, 4C, 5C, and 6C show the cross-sectional views of the drain terminal section 113 in FIG. 1 along the line C-C′, respectively.
FIGS. 3A, 3B, and 3C show the state where a patterned photoresist film 108 is formed prior to etching. In this state, the patterned gate layer 102 is formed on the glass plate 101. The gate insulating layer 103 is formed on the plate 101 to cover the gate layer 102. The patterned drain layer 105 is formed on the gate insulating layer 103. The passivation layer 106 is formed on the gate insulating layer 103 to cover the drain layer 105. The photoresist film 108 with a predetermined pattern is formed on the passivation layer 106.
FIGS. 4A, 4B, and 4C show the state after etching under the ordinary etching condition, where the gate terminal section 111, the contact hole section 109, and the drain terminal section 113 are selectively etched using the photoresist film 108. In the gate terminal section 111, as shown in FIG. 4A, the passivation layer 6 and the gate insulating layer 103 are selectively etched to expose the underlying gate layer 2, forming a contact hole 114. In the contact hole section 109 and the drain terminal section 113, as shown in FIGS. 4B and 4C, the passivation layer 6 is selectively etched to expose the underlying drain layer 5, forming contact holes 109a and 115, respectively. All the contact holes 114, 109a, and 115 have tapered etching profiles as desired. In this etching process, the photoresist film 108 also is etched horizontally and vertically, resulting in an etched photoresist film 108a. 
FIGS. 5A, 5B, and 5C show the state after etching under the raised (i.e., higher-speed) etching condition. In the gate terminal section 111, as shown in FIG. 5A, the passivation layer 6 and the gate insulating layer 103 are over-etched. In the contact hole section 109 and the drain terminal section 113, as shown in FIGS. 5B and 5C, the passivation layer 6 is over-etched. All the contact holes 114, 109a, and 115 do not have tapered etching profiles as desired. Instead, they have square or inverted tapered profiles. The photoresist film 108 also is etched horizontally and vertically, resulting in an etched photoresist film 108a. 
FIGS. 6A, 6B, and 6C show the state after etching under the raised (i.e., higher-speed) etching condition and forming the pixel electrode layer 107 on the passivation layer 106. In the gate terminal section 111, as shown in FIG. 6A, the pixel electrode layer 107 is divided or cut on the inner sidewall of the passivation layer 106. This is because the inner sidewall of the passivation layer 106 is too steep (in other words, the inner sidewall is approximately square or vertical) due to over-etching in the contact hole 114. Similarly, in the contact hole section 109 and the drain terminal section 113, as shown in FIGS. 6B and 6C, the pixel electrode layer 107 is divided or cut on the inner sidewall of the passivation layer 106. This is because the passivation layer 6 has inverted tapered profiles due to over-etching in the contact holes 109a and 115.
As seen from the above explanation when a raised (i.e., higher-speed) dry etching condition is applied to the etching process in fabrication of the first prior-art TFT array substrate 100, the raised etch rate of the photoresist mask 108 is unable to follow the raised etch rates of the passivation layer 106 and the gate insulating layer 103. As a result, the etching profile of the passivation layer 106 is likely to be square or inverted tapered, as shown in FIGS. 5A to 5C.
It is necessary that the pixel electrode layer 107 is placed on the inner sidewalls of the contact hole 114 of the passivation layer 106 and the gate insulating layer 103, and that the layer 107 is electrically connected to the underlying gate layer 102 in the gate terminal section 111. Similarly, the pixel electrode layer 107 needs to be placed on the inner sidewall of the contact hole 109a or 115 of the passivation layer 106, and needs to be electrically connected to the underlying drain layer 105 in the contact hole section 109 or drain terminal section 115. However, the pixel electrode layer 107 is divided or cut, as shown in FIGS. 6A to 6C when a raised dry etching condition is applied. Accordingly, point defects or the like will occur in the first prior-art LCD device.
Next, another prior art is explained below with reference to FIGS. 7 and 8.
A method of forming a tapered etching profile in a dry etching process is disclosed in the Japanese Patent Publication No. 7-312425 published in November 1995, which is termed the second prior art. In this method, a layer constituting a TFT has a multilayer structure comprising two or more sublayers, where the etch rates of the sublayers vary monotonously according to their stacking orders. The etch rate of the sublayer disposed at the highest level is maximum and the etch rate of the sublayer disposed at the lowest level is minimum. The thickness of the sublayer disposed at the lowest level is set in the range from 5% to 20% of the whole thickness of the said layer.
FIGS. 7 and 8 are cross-sectional views of the second prior-art layer with the above-described multiple-layer structure, which show the relationship between the tapered etching profile and the thickness of the two sublayers of the said layer.
As shown in FIG. 7, a layer 220 of a TFT is formed by a lower sublayer 221 and an upper sublayer 222. The lower sublayer 221 is formed on a glass plate 201. The upper sublayer 222 is formed on the lower sublayer 221. The etch rate of the lower sublayer 221 is less than that of the upper sublayer 222. In other words, the lower etch-rate sublayer 221 is disposed on the plate 201, and the higher etch-rate sublayer 222 is disposed on the lower etch-rate sublayer 221.
When the layer 220 with the two-layer structure shown in FIG. 7 is etched by a dry etching process, first, etching of the higher etch-rate sublayer 222 is started. When the etching of the sublayer 222 is completed, etching of the lower etch-rate sublayer 221 is started. Therefore, in the etching process of the lower etch-rate sublayer 221, the higher etch-rate sublayer 222 is over-etched not only vertically but also horizontally. As a result, the higher etch-rate sublayer 222 has a tapered etching profile, in other words, the inner sidewall of the sublayer 222 is tapered, as shown in FIG. 8.
Here, it is important for dry etching that the range of the thickness d1 of the lower etch-rate sublayer 221 to the whole thickness D of the layer 220. Specifically, it is preferred that the thickness d1 is in the range of 5% to 20% of the whole thickness D, because the obtainable taper angle is in the range of 10° to 70°. This means that the relationship between the lower etch-rate sublayer 221 (thickness: d1) and the higher etch-rate sublayer 222 (thickness: d2) is preferably set to satisfy the condition that the thickness d1 is in the range of 5% to 20% of the whole thickness D (=d1+d2).
If the thickness d1 of the lower etch-rate sublayer 221 is greater than 20% of the whole thickness D, the time for etching the lower etch-rate sublayer 221 is too long and therefore, the horizontal etching amount of the higher etch-rate sublayer 222 is too much. In this case, the etching profiled of the sublayer 222 is likely to be inverted tapered.
On the other hand, if the thickness d1 is less than 5% of the whole thickness D, the time for etching the lower etch-rate sublayer 221 is too short and therefore, the horizontal etching amount of the higher etch-rate sublayer 222 is insufficient. In this case, the etching profiled of the sublayer 222 is unlikely to have a desired tapered angle.
For wet etching, similarly, it is preferred that the thickness d1 of the lower etch-rate sublayer 221 is in the range of 50% to 90% of the whole thickness D. In addition, the taper angle of the tapered etching profile is controllable by changing the thickness ratio (d2/d1) between the lower etch-rate sublayer 221 and upper etch-rate sublayer 222, the etch rate ratio thereof, and the etching condition.
As explained above, with the first prior art TFT array substrate 100 shown in FIG. 1 to FIG. 6C, when a raised (i.e., higher-speed) dry etching condition is applied to the dry etching process in fabrication of the substrate 100, the raised etch rate of the photoresist mask 108 is unable to follow the raised etch rates of the passivation layer 106 and the gate insulating layer 103. As a result, the etching profile of the passivation layer 106 is likely to be square or inverted tapered. Accordingly, the pixel electrode layer 107, which is disposed on the passivation layer 106 and electrically connected to the gate layer 102 or the drain layer 105, tends to be divided or cut, resulting in a problem of point defects or the like of the LCD device.
With the second prior art shown in FIGS. 7 and 8, when the second prior-art method is applied to the formation of the passivation layer 106, the thickness ratio of the higher etch rate sublayer (which means its coarse quality) to the whole thickness of the passivation layer 106 will be large. Therefore, there is a problem that the protection function (e.g., moisture proof) of the passivation layer 106 itself degrades. To obtain a sufficient protection effect, the whole thickness of the passivation layer 106 may be increased. If so, however, another problem that the throughput of the layer formation (deposition) and etching apparatuses reduces will occur.
In addition, as described above, the second prior art discloses an application to wet etching, where the thickness d1 of the lower etch-rate sublayer 221 is preferably set in the range of 50% to 90% of the whole thickness D. However, if wet etching is used, the contact hole is likely to be expanded due to side etching by an impregnated etching solution to a gap between the photoresist film 108 and the passivation layer 106 when the adhesion strength (i.e., close contact) between the photoresist film 108 and the passivation layer 106 is insufficient locally or entirely. For example, if an etching solution seeps to the outside of the drain electrode 105d, the underlying gate insulating layer 103 is etched, thereby unsticking the drain layer 105 from the gate insulating layer 103.
Furthermore, if a damaged area (e.g., a damaged area caused by plasma in the dry etching process for the channel region of the TFT 112) is formed through an intermediate process at the interface between the passivation layer 106 and the gate insulating layer 103, the etching profile of the passivation layer 106 is likely to be inverted tapered due to side etching in the damaged area when a wet etching is used. Accordingly, the conductive layer (i.e., the pixel electrode layer 107) formed on the passivation layer 106 tends to be divided.
In recent years, according to the expanding substrate size, etch uniformity control in the existing wet etching apparatuses has become difficult. At the same time, there is a danger that liquid medicines such as hydrofluoric (HP) acid need to be used in large quantities in wet etching. In addition, since an obtainable etch rate in wet etching is extremely lower than that in dry etching, the use of wet etching has decreased for etching the passivation layer 106 and the gate insulating layer 103.